1. Field of the Invention
The present invention relates to a method of fabricating a thin film transistor to be used as a switch of an active matrix liquid crystal display and the like.
2. Description of the Background Art
FIG. 1H is a cross-sectional view of a conventional thin film transistor having an LDD (lightly doped drain) structure, which is fabricated through the process steps shown in FIGS. 1A to 1G. Such a thin film transistor is disclosed in, for example, Japanese Patent Publication No. 3-38755.
In FIG. 1H, reference numeral 1 designates an insulating substrate; 2 designates a Si thin film formed on the insulating substrate 1 and serving as a channel; 3 designates a gate insulating film formed on the Si thin film 2; and 4 designates a gate electrode formed on the gate insulating film 3. Reference numerals 5 designates lightly doped drain (LDD) regions doped with impurities such as phosphorus, boron or the like at a low concentration in the Si thin film 2; and 6 designates source/drain regions doped with impurities such as phosphorus, boron or the like at a high concentration in the Si thin film 2.
Reference numeral 7 designates a source electrode composed of a metal thin film; and 8 designates a drain electrode composed of a metal thin film. Reference numerals 9 designates contact holes for connecting the source and drain electrodes 7 and 8 to the source/drain regions 6.
Description will now be given hereinafter of a method of fabricating the thin film transistor of FIG. 1H with reference to FIGS. 1A to 1G.
The Si thin film 2 serving as a channel layer is initially formed on the insulating substrate 1, as shown in FIG. 1A. The gate insulating film 3 made of SiO.sub.2 is formed in a thickness of 1400 .ANG., for example, by means of a thermal oxidation or sputtering technique, as shown in FIG. 1B. A phosphorus doped Si thin film is formed on the gate insulting film 3 and is then patterned to form the gate electrode 4, as shown in FIG. 1C. Using the gate electrode 4 as a mask, ion implantation is carried out with phosphorus at a low concentration to form the source/drain regions 5 in the Si thin film 2, as shown in FIG. 1D.
A pattern 10 that is wider than the gate electrode 4 is formed on the gate electrode 4, using a photoresist, as shown in FIG. 1E. Using the photoresist pattern 10 as a mask, the Si thin film 2 is ion implanted with phosphorus at a high concentration. This provides the LDD regions 5 doped with phosphorus at the low concentration and the source/drain regions 6 doped with phosphorus at the high concentration, as shown in FIG. 1F.
The contact holes 9 are formed in the gate insulating film 3, as shown in FIG. 1G. The source electrode 7 and the drain electrode 8 are simultaneously formed through the contact holes 9, as shown in FIG. 1H. This completes the thin film transistor having the LDD structure.
If the low concentration ion implantation of FIG. 1D is not executed, the regions 5 in FIG. 1H become an intentionally undoped region, to thereby achieve a thin film transistor having an offset structure, as shown in FIG. 2.
In operation, variation in a voltage applied across the source and gate electrodes 7 and 4, with a voltage applied across the source and drain electrodes 7 and 8, enables a drain current flowing between the source and drain electrodes 7 and 8 to vary. Thus, the thin film transistor of FIG. 1H may be used as a switching element.
For using the thin film transistor as a switching element of an active matrix liquid crystal display, an off-state resistance of the thin film transistor is required to be at least not less than the resistance of a liquid crystal element. This necessitates reduction in the off-state drain current of the transistor.
In particular, when a polycrystalline Si film is used as the Si thin film 2 for channel formation in order to increase an on-state drain current, a field enhanced emission current flows due to the presence of grain boundaries in the polycrystalline Si film, resulting in an increase in the off-state drain current. The off-state drain current is generally believed to be proportional to the number of dangling bonds in grain boundary and to an electric field strength in the vicinity of the drain.
For the purpose of reducing the electric field strength in the vicinity of the drain, the LDD regions 5 doped at the low impurity concentration are formed in the transistor of FIG. 1H, to increase the width of a depletion layer formed between the Si thin film 2 and the source/drain regions 6. As a result, the LDD structure capable of reducing the off-state drain current is achieved.
The conventional thin film transistor having the LDD structure has required two photolithography process steps in order to separately make the low impurity concentration regions 5 and the high impurity concentration regions 6. As the length of the low impurity concentration regions 5 grows large, the resistance elements of the regions 5 increase, resulting in disadvantageous reduction in the on-state drain current of the thin film transistor. Preventing this necessitates an alignment accuracy between the gate electrode 4 and the resist 10 in FIG. 1E. In particular, as the impurity concentration of the regions 5 doped at the low concentration is reduced for reducing the off-state drain current, the resistance elements of the low impurity concentration regions 5 increase to cause the reduction in the on-state drain current. Therefore an improvement is required in alignment accuracy between the gate electrode 4 and the resist 10.
Another approach is to make an offset structure in which impurities are not introduced intentionally into the low impurity concentration regions 5 to reduce the on-state drain current, as shown in FIG. 2. This attempt, however, increases the resistance of the channel region 2, which decreases the on-state drain current without accurate control of the channel length. However, accurate exposure has been quite difficult. A large-sized device such as a liquid crystal display including a display portion having a diagonal line over several inches in length has not met the foregoing demands because there is no exposing device capable of large area exposure and having a high alignment accuracy.